Normally, when a program running in a CPU or other PU (Central or other Processing Unit) is waiting upon some event external to the program, the program will run a poll loop where it will keep reading an event register, utilized by the PU in connection with the program, until the event that it is waiting upon occurs. While the program is operating the PU in polling the event register, the PU is not doing useful work although it is still running and all associated components, such as temporarily idle math logic units, are burning power.
Present day computer system processors are monitored by the operating system and put to sleep based upon inactivity and an interrupt is used to reawaken the processor. Involving the operating system is inefficient and is especially so when a multiprocessor environment is contemplated. Further, transactions such as processor-to-processor communications and “suspend” are not typically handled with interrupts.
It would thus be desirable to establish a method of and a PU control mechanism for maintaining at least some of the temporarily idle associated components of the PU, or alternatively the entire PU, into a low power, sleep or other power suspended state during times when the PU is not providing useful computations or other processor actions.